Ventana tempts hyperscalers with custom RISC-V server chip • The Register

Ventana tempts hyperscalers with custom RISC-V server chip • The Register

RISC-V Summit Ventana Micro Systems is set to unveil a family of datacenter-class processors based on the RISC-V architecture, which it claims will allow buyers to customize the chips to meet their requirements by combining Ventana’s CPU cores with other silicon.

To be officially announced at this week’s RISC-V Summit in San Jose, Ventana’s Veyron V1 is being hailed by the company as the first RISC-V chip to be competitive against existing datacenter processors in terms of single thread performance.

The company came out of stealth mode last year.

“Our main goal was to create a world class, high performance RISC-V processor that’s going to be competitive relative to everything else that’s out there in the market today,” Ventana founder and CEO Balaji Baktha told us.

High single thread performance is a key requirement for Ventana’s target market: hyperscalers. Another feature intended to please them is the processor architecture, which lets customers to assemble their own system-on-chip (SoC) design from chiplets, allowing them to add custom silicon to one or more chiplets with Veyron V1 cores.

This approach apparently owes much to Cisco, which was an early investor in Ventana, according to Baktha.

“We realized chiplets were the best way to productize this to allow hyperscalers to customize the end SoC to fit their particular workload needs,” he said. “That was the founding premise, and we were able to work with various business units within Cisco to gather up all of the hardware requirements, all of the software requirements, and proactively meld them together to come up with a solution that they would see as acceptable.”

AWS and Google know how to build an SoC because they have already done it, Baktha pointed out, citing examples such as the AWS Graviton processors.

“But building CPU cores, that’s another story, they don’t have those kind of teams in-house,” he claimed, “So if you can deliver the compute portion of it in the form of a chiplet as a known good die, that removes the hurdle of them having to do that in-house.”

What Ventana is offering the hyperscalers is a kit from which they can assemble their own SoCs to their own requirements. This comprises one or more Veyron compute chiplets, a reference I/O hub chip design, and the die-to-die interconnect technology to tie it all together.

“All they have to do is take the I/O hub, and customize it. Customizing that I/O hub is as simple as dropping in an accelerator or whatever you have seen working on an FPGA, and all of a sudden they have a customized SoC,” Baktha said, claiming that this approach would save hyperscale customers at least $75 million and a minimum of two years of design development cycle time to create a custom SoC.

Another advantage, according to Baktha, is that Ventana’s die-to-die interconnect is parallel, cutting out unwanted latency.

“Until now, everybody has done a serialised interconnect, mostly a SerDes-based die-to-die interconnect. We have a parallel die-to-die interconnect. Why is that important? Serial interconnects take about 120 to 130 nanoseconds to communicate between them. With parallel, that latency is seven nanoseconds, which is very similar to a single die monolithic design,” he claimed.

In fact, Ventana is pursuing three routes to market; the first is to supply both the compute chiplets and I/O hub, the second is to let the customer build their own custom I/O hub, perhaps supporting HBM memory for high performance computing, for example, and the third is IP licensing, in case a customer wants a smaller number of compute cores, for example.

That Ventana compute chiplet comprises 16 RISC-V cores with 48MB of shared L3 cache, clocked at 3.6GHz. Initially, the chiplets will be manufactured by TSMC using a 5nm production node, while the I/O hub or other components can be manufactured using less cutting edge nodes, perhaps 12nm or 16nm.

Customers can combine the compute chiplets to build an SoC with up to 192 cores, according to Ventana.

The company also claims to have a number of chiplet partners it has assembled that can provide chiplets with other functions or implement an SoC for customers. The list includes Apex Semiconductor, Silicon Box, FLC Technology Group and Bolt Graphics.

Meanwhile, the beauty of the RISC-V ecosystem is that there is already software support from the open source community, including Linux distributions such as Ubuntu and Debian, along with applications such as Ceph storage, NGINX, MySQL, OpenJDK and Redis.

Another claim is that because it’s a clean slate design, Ventana has been able to avoid the kind of flaws that have led to side-channel attacks of the sort seen in the Spectre or Meltdown exploits in other processors. We suspect this kind of claim might be tempting fate.

Andrew Buss, IDC Senior Research Director for Europe, told us that this launch is coming at an interesting time because of the emergence of Arm-based solutions into the public cloud platforms, representing a divergence from the traditional x86 dominance.

“The software ecosystem is maturing and we’re moving to a situation where compatible code and also multi-platform portable code is making this feasible,” he said.

For RISC-V, it may look like it is late to the party, and the momentum is now with Arm. However, “the same trends enabling Arm will also work for RISC-V and they need to be investing in getting the same ecosystem support to make it viable,” Buss added.

But Arm has not really helped its case with the Qualcomm lawsuit, according to Buss, showing that in many cases, Arm is quite restrictive in what it will license and this can limit customization options.

Manoj Sukumaran, Omdia Principal Analyst for DataCenter Compute & Networking, said there is growing interest in alternative CPU architectures because geopolitical and trade tensions are causing technology insecurity in several countries.

He told us that he thought it likely that the Ventana chip would serve as an R&D platform for the RISC-V software stack, and may not see much major customer adoption.

“The software ecosystem for RISC-V is still very nascent and that will be the biggest barrier for adoption. But it is definitely a great start, having a platform designed for server workloads creates a lot of momentum for software development efforts,” he said.

With the Veyron V1 now officially launched, Ventana said it expects that early customers will have first production silicon by Q2 or Q3 2023.

The company is already working on a second generation product, which it expects to deliver a large instruction per clock (IPC) performance boost compared to this design and may see the light of day as soon as 2024.

“In a way, we’ve parallelized the development process to allow us to kind of drive v2 design very quickly, with samples coming about a year after the samples for v1,” Baktha said. ®

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